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general description the max5039/MAX5040 provide intelligent control to power systems where two supply voltages need track- ing. these cases include powerpc , dsp, and asic systems, which require a lower core voltage supply and a higher i/o voltage supply. the max5039/MAX5040 control the output voltage of the core and i/o supplies during power-up, power- down, and brownout situations. they ensure that the two power supplies rise or fall at the same rate, limiting the voltage difference between the core and i/o sup- plies. this eliminates stresses on the processor. the max5039/MAX5040 shut down both the core and i/o supplies if either one is shorted or otherwise fails to come up. the MAX5040 provides a power-ok (pok) signal that signals the processor if the core supply, the i/o sup- ply, and the system bus supply (v cc ) are above their respective specified levels. the max5039/MAX5040 are targeted for nominal bus v cc voltages from 4v to 5.5v. the max5039/MAX5040 work with core volt- ages ranging from 800mv to about 3v (depending on the gate-to-source turn-on threshold of the external n- channel mosfet) and i/o voltages ranging from v core to 4v. the max5039/MAX5040 provide tracking control of the i/o and core voltages using a single external n-channel mosfet connected across them. this mosfet is not in series with the power paths and does not dissipate any additional power during normal system operation. the external mosfet is only on for brief periods during power-up/power-down cycling so a low-cost, small-size mosfet with a rating of 1/4th to 1/8th of the normal supply current is suitable. the max5039/MAX5040 are offered in space-saving 8-pin ?ax and 10-pin ?ax packages, respectively. applications powerpc systems embedded dsps and asics embedded 16- and 32-bit controller systems telecom/base station/networking features provide tracking of two external power supplies during power-up and power-down compatible with a wide range of external power supplies independent of output power bus voltage undervoltage lockout enables/ disables core and i/o supplies together detect short circuit on v core and v i/o , disable core and i/o supplies in either case output undervoltage monitoring pok status (MAX5040) operating v cc supply voltage range: 2.5v to 5.5v i/o voltage range: v core to 4v core voltage range: 0.8v to v i/o max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics ________________________________________________________________ maxim integrated products 1 ordering information 19-2461; rev 0; 5/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available powerpc is a registered trademark of ibm corp. part temp range pin-package max5039 eua-t -40 c to +85 c 8 max MAX5040 eub-t -40 c to +85 c 10 max v cc v cc core core i/o i/o with max5039 or MAX5040 without max5039 or MAX5040 power-on and power-off with and without voltage tracking typical operating circuit and pin configurations appear at end of data sheet.
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 2.5v to 5.5v, v uvlo = 2v, v core = 1.8v, v i/o = 2.5v, v core_fb = 1v, v i/o_sense = 2v (MAX5040 only), t a = -40 c to +85 c, unless otherwise specified. typical values are at v cc = 5v, t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd) v cc , ndrv, sdo , and pok ..................................-0.3v to +14v core_fb, uvlo, i/o_sense, i/o, core ..........-0.3v to +4.25v all pins to v cc (except pok)............................................. +0.3v ndrv continuous current .................................................50ma continuous current, all other pins .....................................20ma continuous power dissipation (t a = +70 c) 8-pin max (derate 4.5mw/ c above +70 c) .............362mw 10-pin max (derate 5.6mw/ c above +70 c) ...........444mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units external supply conditions v cc v cc (note 1) 2.5 5.5 v v cc supply current i cc 1.3 2.25 ma lowest v cc where sdo is valid v cclo (note 2) 0.9 v sdo output low voltage at v cc = v cclo v uvlo = v cc = v cclo , i sdo = 50a, measure v sdo (note 2) 0.4 v v cc rising 2.43 2.5 v cc ic turn-on voltage threshold (note 3) hysteresis 0.05 v core voltage range v core i/o and core valid, v cc = 5.5v (notes 4, 5) 0.8 v i/o v i/o and core valid (note 5) v cc > 4v v core 4.0 i/o voltage range v i/o i/o and core valid (note 5), 2.5v v cc 4v v core v cc v user-programmable undervoltage lockout v uvlo rising 1.200 1.230 1.260 v uvlo trip threshold v uvcc hysteresis 110 mv uvlo input bias current v uvlo = 2v 250 na core and i/o regulation core feedback, core_fb, and reference voltage v c_ref 784 800 816 mv c o re reg ul ator lar g e- s i g nal gai na v core_fb to ndrv 60 db core regulator crossover frequency core_fb to ndrv 400 khz v cc 3v 40 80 pullup strength, v i/o = 1v, v core = 2v, i ndrv = -10ma v cc 2.5v 50 100 v cc 3v 13 27 ndrv output resistance pulldown strength, v i/o = 2v, v core = 1v, i ndrv = 10ma v cc 2.5v 17 35 ? v core - v i/o , v i/o falling 60 90 130 i/o-core comparator trip threshold (note 6) v th v core - v i/o , v i/o rising -15 0 15 mv
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 2.5v to 5.5v, v uvlo = 2v, v core = 1.8v, v i/o = 2.5v, v core_fb = 1v, v i/o_sense = 2v (MAX5040 only), t a = -40 c to +85 c, unless otherwise specified. typical values are at v cc = 5v, t a = +25 c.) parameter symbol conditions min typ max units core pulldown resistance v core = 1.8v, v uvlo = 1v, v cc = 2.5v 20 50 ? monitor outputs sdo output low voltage v olsdo i sdo = 1.8ma, v uvlo = 1v, v cc = 2.5v 0.4 v i sdo = -1.0ma, v cc = 4v v cc - 0.4v sdo output high voltage v ohsdo i sdo = -1.0ma, v cc = 2.5v v cc - 0.55v v v i/o_sense rising 1.200 1.230 1.260 v i/o_sense trip threshold v i/o_ref hysteresis 25 mv pok output low voltage v olpok i pok = 1.8ma 0.4 v pok leakage current i lpok v pok = v cc 1.0 a pok glitch rejection time t pok (note 7) 50 s fault time t fault (note 8) 10 15 20 ms i/o and core inputs i/o input bias current v i/o = 1v 20 a core input bias current v core = 1v 20 a i/o_sense input bias current v i/o_sense = 0.8v 250 na core_fb input bias current v core_fb = 1.2v 300 na note 1: v cc slew-rate limited to 30v/s. note 2: sdo automatically goes low when the uvlo pin drops below its threshold (or v cc drops below 2.5v). sdo remains low as v cc falls. for some v cc below v cclo sdo may float. note 3: this undervoltage lockout disables the max5039/MAX5040 at v cc voltages below which the device cannot effectively oper- ate. when v cc drops below the threshold, sdo goes low, the bleeder turns off, and pok is high impedance. note 4: in order to regulate correctly, v cc must be higher than v core plus the turn-on voltage of the external n-channel mosfet. note 5: i/o and core valid mean the voltages on these pins have settled within their target specifications for normal operation. note 6: core and i/o supplies rise and fall rates must be limited to less than 6.6v/s. note 7: pok does not deassert for glitches less than t pok . note 8: a fault condition is latched when either of the two following conditions maintains for longer than t fault : v core_fb < v c_ref (i.e., v core is less than its set point) v i/o < v core a fault condition forces sdo and pok (MAX5040 only) low. core discharges to gnd through 20 ? while v cc > 2.5v. cycle uvlo or v cc low, then high, to clear a fault.
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 4 _______________________________________________________________________________________ typical operating characteristics (v cc = 5v, v core = 1.8v, v i/o = 3.3v, t a = +25 c, unless otherwise specified.) system power-up/power-down (v i/o rising before v core ) max5039/40 toc01 5ms/div v cc 5v/div ndrv 5v/div sdo and pok 5v/div i/o and core 1v/div v cc ndrv core i/o pok sdo system power-up/power-down without max5039/MAX5040 (v i/o rising before v core ) max5039/40 toc02 5ms/div v cc 5v/div i/o and core 1v/div core i/o v cc 796 799 798 797 800 801 803 802 804 2.5 4.5 3.5 5.5 max5039/40 toc03 core_fb reference (v c_ref ) vs. v cc and temperature v cc (v) core_fb reference (mv) t a = +85 c t a = +25 c t a = -40 c -20 10 0 -10 20 30 50 40 60 100 10k 1k 100k core regulator loop bode plot (see figure 9) frequency (hz) gain (db) 0 -60 -30 90 60 30 120 150 180 phase margin (degrees) v cc = 5v, v i/o = 3.3v, v core = 1.8v at 1a phase gain max5039/40 toc04 0 150 100 50 200 250 350 300 400 02 134 max5039/40 toc05 v sdo vs. i sdo(sink) v cc = 2.5v i sdo(sink) (ma) v sdo (mv) t a = -40 c t a = +85 c t a = +25 c 0 150 100 50 200 250 350 300 400 0 0.2 0.1 0.3 0.4 0.5 0.6 max5039/40 toc06 v sdo vs. i sdo(sink) v cc = 0.9v i sdo(sink) (ma) v sdo (mv) t a = +85 c t a = +25 c t a = -40 c
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics _______________________________________________________________________________________ 5 1.230 1.236 1.234 1.232 1.238 1.240 1.244 1.242 2.5 3.5 3.0 4.0 4.5 5.0 5.5 max5039/40 toc10 uvlo rising threshold vs. v cc v cc (v) v uvcc (v) t a = +85 c t a = -40 c t a = +25 c 90 95 100 105 110 115 2.5 3.5 3.0 4.0 4.5 5.0 5.5 max5039/40 toc11 uvlo hysteresis vs. v cc v cc (v) uvlo hysteresis ( mv) t a = +85 c t a = -40 c t a = +25 c 1.230 1.233 1.232 1.231 1.234 1.235 1.237 1.238 1.239 1.236 2.5 3.5 3.0 4.0 4.5 5.0 5.5 max5039/40 toc12 i/o_sense threshold (v i/o_ref ) vs. v cc v cc (v) v i/o_ref (v) t a = -40 c t a = +85 c t a = +25 c 20 23 22 21 24 25 26 27 28 29 30 2.5 3.5 3.0 4.0 4.5 5.0 5.5 i/o_sense hysteresis vs. v cc max5039/40 toc13 v cc (v) i/o_sense hysteresis (mv) t a = +85 c t a = +25 c t a = -40 c 43 45 44 46 47 48 49 2.5 3.5 3.0 4.0 4.5 5.0 5.5 pok glitch rejection vs. v cc max5039/40 toc14 v cc (v) glitch rejection time ( s) t a = +85 c t a = +25 c t a = -40 c typical operating characteristics (continued) (v cc = 5v, v core = 1.8v, v i/o = 3.3v, t a = +25 c, unless otherwise specified.) 0 1 2 3 4 5 0 1.0 0.5 1.5 2.0 2.5 3.0 max5039/40 toc07 v sdo vs.i sdo(source) i sdo(source) (ma) v sdo (v) t a = -40 c v cc = 4.5v t a = +85 c t a = +25 c v cc = 2.5v t a = -40 c t a = +85 c t a = +25 c 0 150 100 50 200 250 300 350 400 450 500 08 4121620 ndrv pulldown strength max5039/40 toc08 i ndrv (ma) v ndrv (mv) t a = +85 c v cc = 5v t a = -40 c t a = +25 c t a = +85 c v cc = 2.5v t a = +25 c t a = -40 c 0 2 1 3 4 5 6 08 4121620 ndrv pullup strength max5039/40 toc09 i ndrv (ma) v ndrv (v) t a = -40 c v cc = 5v t a = +85 c t a = +25 c v cc = 2.5v t a = -40 c t a = +85 c t a = +25 c
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 6 _______________________________________________________________________________________ pin description pin max5039 MAX5040 name function 11 sdo active-low shutdown output. connect sdo to active-low shutdown input of both core and i/o supplies. sdo is high when v uvlo v uvcc and v cc 2.5v and if there is no fault. 22v cc supply voltage input. connect v cc to the supply voltage that powers the core and i/o supplies. bypass v cc to gnd with a 1f capacitor. 3 3 uvlo user-programmable undervoltage lockout. connect to midpoint of the voltage-divider from v cc to gnd. set trip point below minimum v cc voltage. v uvlo v uvcc forces sdo and pok (MAX5040 only) low. use uvlo as an active-low shutdown input to turn on/off the core and i/o supplies if desired. 4 4 gnd ground 5 7 core_fb core feedback input. connect core_fb to the midpoint of the voltage-divider from core to gnd. the max5039/MAX5040 keep core_fb from dropping below v c_ref by controlling ndrv. any time v core_fb falls below v c_ref , ndrv rises above ground to a voltage sufficient to maintain v core_fb = v c_ref . if v core_fb remains below v c_ref for longer than t fault , a latched fault is generated. during a fault, max5039/MAX5040 continue to regulate core_fb. three things halt regulation of core_fb: if v cc falls below 2.5v, ndrv goes to gnd. if i/o falls below core, ndrv goes to v cc . if v core_fb rises above v c_ref , ndrv goes to gnd. 6 8 core core supply sense input. connect core to the core output voltage. if v core > v i/o , ndrv goes to v cc , pok (MAX5040 only) goes low. fault is latched if this condition lasts longer than t fault . a 20 ? bleeder discharges core to gnd whenever sdo is low and v cc > 2.5v. 7 9 i/o i/o supply sense input. connect to i/o output voltage. if v core > v i/o , ndrv goes to v cc , pok (MAX5040 only) drives low. a fault is latched if this condition lasts longer than t fault . 8 10 ndrv n-channel mosfet gate driver. connect ndrv to the gate of the external n-channel mosfet that shunts i/o to core. 5 i/o_sense i/o feedback input. use a resistor-divider to divide v i/o and apply to this pin. when v i/o_sense v i/o_ref , pok drives low. i/o_sense can also be used to monitor any other voltage. 6 pok open-drain power-ok output. pok drives low when any condition below is true: v cc 2.5v v uvlo v uvcc v core_fb v c_ref v i/o v core v i/o_sense v i/o_ref max5039/MAX5040 latches a fault
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics _______________________________________________________________________________________ 7 performance during typical operation scope shots are of the MAX5040 ev kit. figures 1 through 8 demonstrate system performance of the MAX5040 under various power-up, power-down, and fault conditions. in some cases (described in detail below), startup or shutdown of the i/o and core sup- plies were purposely delayed with respect to each other to simulate possible system operating conditions. in figure 1 (with MAX5040), v cc ramps up slowly and the i/o supply comes up before the core supply. as soon as v cc rises above 2.5v (at about 7.5ms) ndrv goes to v cc shorting the i/o and core supplies togeth- er. when v cc rises above 4.5v (bringing v uvlo above v uvcc ), sdo goes high enabling the i/o and core supplies. although the core pwm supply turns on 5ms after the i/o pwm supply, both supply voltages come up together because ndrv is held at v cc , shorting the sup- plies together through the n-channel fet. the i/o supply supports both the i/o line and the core line. once v core rises close to its set point, ndrv falls to around 2.8v to regulate v core at its set point. at around 22ms, the core supply comes up, ndrv goes to gnd, and pok goes high. on power-down, when v cc drops low enough to bring v uvlo below v uvcc , sdo immediately falls, turning the i/o and core supplies off. simultane- ously, pok falls, indicating power-down to the proces- sor. when the i/o voltage drops below the core voltage, ndrv goes to v cc (at around 36ms), shorting the supplies together. ndrv remains at v cc until v cc falls below 2.5v and then it returns to gnd. in figure 2 (without MAX5040), v cc ramps up slowly and the core and i/o supplies are turned on when v cc exceeds 2.5v. the i/o voltage comes up before the core voltage. there is a 3.3v difference between the i/o and core supplies for about 4ms before the core supply finally comes up. when v cc powers down, i/o remains high for about 10ms after core reaches gnd. in figure 3 (with MAX5040), v cc ramps up slowly and the core supply comes up before the i/o supply. as soon as v cc rises above 2.5v (at about 7.5ms), ndrv goes to v cc , shorting the i/o and core supplies togeth- er. when v cc rises above 4.5v (bringing v uvlo above v uvcc ), sdo goes high, enabling the i/o and core supplies. although the i/o pwm supply turns on 8ms after the core pwm supply, both supply voltages come up together because ndrv is held at v cc , shorting the supplies together through the n-channel fet. the core supply supports both the core line and the i/o line until the i/o supply comes up. at around 23ms, the i/o supply turns on, pulling the i/o voltage above the core volt- age. at this point, the MAX5040 brings ndrv to gnd and pok goes high. on power-down, when v cc drops low enough to bring v uvlo below v uvcc , sdo immedi- ately falls, turning the i/o and core supplies off. simultaneously pok falls, indicating power-down to the processor. when the core voltage drops below its reg- ulation point, ndrv begins to regulate it (at around 30ms). when i/o falls below core, ndrv is pulled up to v cc to short the two supplies together. in figure 4 (without MAX5040), v cc ramps up slowly and the core voltage comes up before the i/o volt- age. it takes about 8ms before the i/o supply finally comes up above the core supply. when v cc powers down, the supplies do not turn off together. core remains high for around 14ms after i/o falls. in figure 5 (with MAX5040), the system power-up is attempted with the core supply held in shutdown. as soon as v cc rises above 2.5v, ndrv goes to v cc , shorting the i/o and core supplies together. next, when v cc rises above 4.5v (bringing v uvlo above v uvcc ), sdo goes high, enabling the i/o and core supplies. both supplies come up together because ndrv is high. note that the core supply is still off; core is held up through the n-channel fet shunt. once v core rises close to its set point, the linear regu- lator holds v core to its set point by regulating ndrv to around 2.8v. after 15ms of regulating core, the MAX5040 latches a fault. sdo goes low, ndrv goes to v cc , and both supplies power down together. pok remains low throughout because a valid operating state was not achieved. in figure 6 (with MAX5040), v cc is set to 5v. toggling uvlo from low to high controls system startup. while uvlo is low and the v cc is 5v, ndrv is high, causing the supplies to be shorted together. when uvlo goes high, sdo also goes high, turning on the core and i/o supplies (at around 3ms). in this example, the i/o sup- ply comes up before the core supply. the MAX5040 regulates core by driving ndrv to about 2.8v until the core supply comes up (at around 7ms), then ndrv falls to gnd and pok goes high. when uvlo is driven low, sdo goes low, disabling the core and i/o sup- plies. ndrv goes to v cc and both supplies power down together. in figure 7 (with MAX5040), v cc is set to 5v. toggling uvlo from low to high controls system startup. while uvlo is low and the v cc is 5v, ndrv is high, shorting the supplies together while they are both off. when uvlo does go high, sdo also goes high, turning on the core and i/o supplies (at around 8ms). in this example, the core supply comes up before the i/o
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 8 _______________________________________________________________________________________ supply. the MAX5040 holds up i/o by driving ndrv to v cc (because the i/o voltage is less than the core voltage) until the i/o supply comes up (at around 16ms). at this point, ndrv goes to gnd and pok goes high. uvlo is driven low (at around 22ms), causing sdo to go low, disabling the core and i/o supplies. the core supply powers down at about 23ms and ndrv goes to 2.8v to regulate the core supply until i/o falls. then ndrv goes to v cc when the i/o voltage falls to the core voltage (at around 36ms). figure 8 (with MAX5040) starts out with the supplies in their normal range. at 3ms, core is shorted to gnd. ndrv goes high, and pok goes low immediately. ndrv shorts the i/o supply to the core supply, bring- ing the supplies down together. after 15ms, the MAX5040 latches a fault and sdo goes low turning off the supplies. detailed description the max5039/MAX5040 voltage-tracking controllers limit the maximum differential voltage between two power supplies during power-up, power-down, and brownout conditions. the devices provide a shutdown output control signal, sdo , which is used to turn on system power-up/power-down (v i/o rising before v core ) 5ms/div v cc 5v/div ndrv 5v/div sdo and pok 5v/div i/o and core 1v/div v cc ndrv core i/o pok sdo figure 1. system power-up/power-down (v i/o rising before v core ) system power-up/power-down without max5039/MAX5040 (v i/o rising before v core ) 5ms/div v cc 5v/div i/o and core 1v/div core i/o v cc figure 2. system power-up/power-down without max5039/ MAX5040 (v i/o rising before v core ) system power-up/power-down (v core rising before v i/o ) 5ms/div v cc 5v/div ndrv 5v/div sdo and pok 5v/div i/o and core 1v/div core i/o v cc pok sdo ndrv figure 3. system power-up/power-down (v core rising before v i/o ) system power-up/power-down without max5039/MAX5040 (v core rising before v i/o ) 5ms/div v cc 5v/div i/o and core 1v/div core i/o v cc figure 4. system power-up/power-down without max5039/ MAX5040 (v core rising before v i/o )
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics _______________________________________________________________________________________ 9 and off the core and i/o power supplies. the max5039/MAX5040 monitor and compare the core and i/o voltages as follows. when the i/o voltage is greater than or equal to the core voltage, max5039/MAX5040 regulate the exter- nal n-channel mosfet as a linear regulator by control- ling ndrv. the linear regulator regulates the core voltage to the value set by the external resistor-divider connected from core to core_fb and gnd (see figures 9 and 10). if the core_fb voltage is far less than its regulation point, v c_ref (800mv), ndrv drives high to v cc , effectively shorting core and i/o together through the external mosfet. if the core_fb voltage equals v c_ref , ndrv goes into regulation mode. if the core_fb voltage is higher than v c_ref , the linear reg- ulator goes into standby mode and pulls ndrv low, turning off the external n-channel mosfet. when the i/o voltage is lower than the core voltage by v th (90mv), the max5039/MAX5040 turn the external n- channel mosfet on by driving ndrv high to v cc . whenever sdo is high, the max5039/MAX5040 track the time that ndrv is in regulation mode or driven high. if ndrv is in regulation mode or driven high for longer than t fault (15ms), a fault occurs and sdo is pulled low. system turn-on/turn-off under uvlo control (v core rising before v i/o ) 5ms/div uvlo 5v/div sdo 5v/div pok 5v/div ndrv 5v/div i/o and core 1v/div core i/o ndrv pok uvlo sdo figure 7. system turn-on/turn-off under uvlo control (v core rising before v i/o ) short-circuit response (core shortened to gnd) 2ms/div ndrv 5v/div sdo 5v/div pok 5v/div i/o and core 1v/div core i/o ndrv pok sdo figure 8. short-circuit response (core shorted to gnd) system fault startup (core supply fails to turn on) 4ms/div v cc 5v/div ndrv 5v/div sdo 5v/div pok 5v/div i/o and core 2v/div core i/o v cc pok ndrv sdo figure 5. system power-up/power-down, fault startup (core supply fails to turn on) system turn-on/turn-off under uvlo control (v i/o rising before v core ) 2ms/div uvlo 5v/div ndrv 5v/div sdo 5v/div pok 5v/div i/o and core 1v/div core i/o ndrv pok uvlo sdo figure 6. system turn-on/turn-off under uvlo control (v i/o rising before v core )
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 10 ______________________________________________________________________________________ i/o_sense gnd core i/o uvlo v cc v cc core_fb ndrv pok fault generator bleed fault 400mv 1.23v 1.23v 800mv sdo r r 15ms timer MAX5040 functional diagram
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics ______________________________________________________________________________________ 11 designing with max5039/MAX5040 the max5039/MAX5040 provide intelligent control to power systems where two power supplies need track- ing. follow the steps below for designing with the max5039/MAX5040: 1) select an appropriate external n-channel mosfet (see the n-channel mosfet selection section). 2) set the core regulation voltage (see the program- ming the core voltage section). 3) set the uvlo voltage trip threshold (see the programming uvlo voltage section). 4) compensate the core linear regulator loop (see the linear regulator compensation section). 5) set the pok voltage trip threshold (MAX5040 only, see the programming i/o_sense voltage section). figures 9 and 10 show an application example. functional description s s d d o o sdo is the shutdown signal output. connect sdo to the core and i/o power-supply shutdown pins. sdo allows the max5039/MAX5040 to control the turning on and off of the external switching regulators or linear reg- ulators that supply the core and i/o voltages. using this single control signal, the max5039/MAX5040 turn the core and i/o power supplies on and off together, minimizing the voltage differential between them. sdo is low when: the voltage on the uvlo pin is below v uvcc (1.230v). v cc is below the ic turn-on voltage threshold (2.43v). a fault condition is detected. the max5039/MAX5040 prevent premature turn-on of the core and i/o power supplies during power-up by actively holding sdo low as soon as v cc rises above 0.9v, provided the condition for sdo to stay low is valid. ndrv ndrv controls the gate of the external n-channel mosfet (which is connected between the i/o and core voltages), as needed, as long as v cc is within its operating range. ndrv is driven high to v cc when v i/o < v core . ndrv regulates the external mosfet as a linear regu- lator when v i/o > v core and v core_fb < v c_ref . ndrv is driven low when v i/o > v core and v core_fb > v c_ref . powerpc/ dsp/asic i/o power supply in in out out v cc c in 1 f c1 100nf c core 100 f c i/o 100 f q1 si9428 so-8 c2 1.5nf r7 25.5k ? 1% r8 10k ? 1% r3 10k ? r4 50 ? r2 10k ? 1% r1 9.53k ? 1% v in (5v) uvlo gnd core_fb core sdo ndrv i/o i/o core v i/o = 3.3v at 2.0a v core = 1.8v at 2.0a core power supply shdn shdn max5039 figure 9. typical application circuit for the max5039
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 12 ______________________________________________________________________________________ uvlo uvlo is a user-programmable undervoltage lockout input. when the uvlo voltage is above v uvcc , the max5039/MAX5040 hold sdo high, given that v cc is within its operating range and there is no fault condition present. when the uvlo voltage falls below v uvcc , sdo is pulled low. use a resistor-divider from the input of the core and i/o power supplies to uvlo to gnd to set the undervoltage lockout (see the typical application circuit ). the max5039/MAX5040 keep the core and i/o power supplies off (through the sdo ) until their input voltage is within its operating range. uvlo can be used to turn off the core and i/o power supplies through sdo . pull the uvlo pin low with an open-collector driver to assert sdo , which turns off the power supplies. active bleeder the max5039/MAX5040 contain an internal 20 ? n- channel mosfet bleeder that connects core to ground. the bleeder turns on whenever the max5039/ MAX5040 hold sdo low and v cc is above the v cc ic turn-on voltage threshold (2.43v). this bleeder assists in discharging the output capacitor(s) during power- down/brownout conditions. the max5039/MAX5040 maintain tight voltage tracking of the core and i/o voltages, as long as v cc is within its operating voltage range. it is important to discharge the output capacitors to ground before v cc drops out of its range. figure 11 illustrates a method to prolong v cc after a power- down/brownout condition. the hold-up capacitor, c hd , holds the voltage at v cc up and provides the power to the max5039/MAX5040 to keep them in operation even after v in has gone down. power-up the max5039/MAX5040 prevent premature turning on of the core and i/o power supplies during power-up by actively holding sdo low as soon as v cc rises above 0.9v, provided the condition for sdo to stay low is valid. the max5039/MAX5040 completely turn on and ndrv is operational when v cc rises above the v cc ic turn-on voltage threshold (2.43v). in this state, the max5039/MAX5040 maintain tight tracking of the core and i/o output voltages. the max5039/ MAX5040 continue to hold sdo low until the uvlo volt- age rises above v uvcc (1.230v). once the uvlo voltage rises above v uvcc , sdo goes high, enabling the core and i/o power supplies at the same time. without voltage tracking, depending on the powerpc/ dsp/asic i/o power supply in in out out v cc c in 1 f c1 100nf c core 100 f c i/o 100 f q1 si9428 so-8 c2 1.5nf r7 25.5k ? 1% r8 10k ? 1% r3 10k ? r4 50 ? r5 13.3k ? 1% r6 10k ? 1% r2 10k ? 1% r1 9.53k ? 1% v in (5v) uvlo gnd core_fb pok core sdo ndrv i/o_sense i/o i/o core gpio v i/o = 3.3v at 2.0a v core = 1.8v at 2.0a core power supply shdn shdn MAX5040 figure 10. typical application circuit for the MAX5040
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics ______________________________________________________________________________________ 13 power supplies startup delay and/or soft-start timing, which are specific to each of the power supplies, core and i/o outputs may not rise at the same time or at the same rate. output loading and capacitance fur- ther separate the two output s rise time. the max5039/MAX5040 help the system to overcome these differences and keeps core and i/o voltages tracking together by controlling ndrv, dynamically driving ndrv high, low, or in regulation mode, depending on the core and i/o voltage condition. normal operation after the power-up period is over, core and i/o output voltages settle to their respective regulated values. the linear regulator formed by max5039/MAX5040 and the external mosfet is turned off. during normal opera- tion, the linear regulator goes into a standby mode and ndrv is driven low. the resistor-divider from core to core_fb to gnd must be set so that the linear regulator regulation voltage is less than the core power-supply regulation voltage. see the programming the core voltage section. during normal operation, the max5039/MAX5040 con- stantly monitor the core, i/o, and core_fb voltages. ndrv responds as needed, according to the condi- tions described in the ndrv section. power-down/brownout or shutdown the max5039/MAX5040 continue to provide tracking for the core and i/o output voltages during power- down/brownout or shutdown. during shutdown (uvlo is pulled below v uvcc ), sdo is pulled low, disabling the core and i/o power supplies together. the core and i/o output voltages start to fall. without voltage tracking, depending on the output capac- itance and loading, core and i/o voltages may not fall at the same rate. similar to the power-up condition, the max5039/MAX5040 keep core and i/o voltages track- ing together by controlling ndrv, dynamically driving ndrv high, low, or in regulation mode, depending on the core and i/o voltage condition. during power-down/brownout, v cc is dropping and the uvlo voltage is also dropping. when the uvlo voltage falls below v uvcc , sdo is pulled low, disabling the core and i/o power supplies. similar to the shutdown condition, the max5039/MAX5040 keep core and i/o voltages together. it is important that v cc remains in its operating voltage range in order to keep the max5039/ MAX5040 operating to provide tracking until the output voltages have discharged to a safe level. figure 11 illus- trates a method to prolong v cc after a power- down/brownout condition. the bleeder circuitry is helpful in this power-down/brownout condition because the bleeder helps speed up the discharge process. fault condition while sdo is high, the max5039/MAX5040 keep track of the time ndrv is driven high or in regulation mode. in a typical system during power-up, power-down/ brownout, and normal operation, the time ndrv is driven high or in regulation mode should last for only a few mil- liseconds. if this time exceeds t fault (15ms), indicating an abnormal condition, a fault is generated. during a fault condition, sdo is driven low and ndrv continues its operation as described in the ndrv section. a fault condition is latched. to clear a fault, toggle v cc and/or uvlo to unlatch and restart the system. output short-circuit condition if any of the outputs are shorted to ground, ndrv is dri- ven high to keep the core and i/o voltages tracking each other. the current through the external mosfet is limited by the current limit provided by the external power supply. if the short-circuit condition lasts more than t fault , a fault is generated, sdo is driven low (which turns off the core and i/o power supplies), and ndrv continues its operation as described in the ndrv section. applications information n-channel mosfet selection the external n-channel mosfet connected between core and i/o power supplies is expected to turn on briefly during power-up and power-down/brownout conditions. during normal operation, this mosfet is turned off. in general, only a small size mosfet is needed. a mosfet capable of carrying 1/4th to 1/8th v cc v in uvlo 10 f max5039 MAX5040 c hd figure 11. circuit prolongs v cc after a brownout/power-down condition
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 14 ______________________________________________________________________________________ of the maximum output current rating of the core or i/o power supplies is adequate. however, care should be taken when selecting this mosfet to make sure it is capable of sustaining all of the worst-case conditions, as well as riding through all of the fault conditions. the following are guidelines for selecting the external n- channel mosfet: 1) mosfet drain-to-source maximum voltage rating: v ds rating > v i/o maximum voltage. 2) mosfet gate-to-source maximum voltage rating: v gs rating > v cc maximum. 3) mosfet gate turn-on threshold voltage: v gs(th) < minimum operating voltage of (v cc - v core ). for example, if v cc minimum operating voltage is 4.5v, core voltage is 1.8v, then v gs(th) < (4.5v - 1.8v) = 2.7v. a mosfet with logic-level gate turn-on threshold voltage is appropriate for this application. 4) determine the maximum current that can go through the mosfet during power-up, power- down/brownout, or output short-circuit conditions. in most cases, this maximum current is the current limit of the core or the i/o power supplies, whichever is larger. choose the mosfet with pulse current rating sufficiently higher than this cur- rent. note that typical mosfet pulse current rating is much larger than its continuous current rating. 5) determine the mosfet maximum r dson such that under worst-case current, the voltage drop across its drain-to-source is within the tracking limit (approximately 400mv for most powerpcs, asics, and dsps). 6) determine the maximum single-shot power dissipa- tion in the mosfet during power-up, or during an output short-circuit condition. considering the fol- lowing cases: when either the i/o or core is shorted to gnd, ndrv is driven high to v cc , turning the mosfet on. the current through the mosfet is the maximum current that the supply not shorted can produce (the core supply maxi- mum current if i/o is shorted or vice versa). depending on which supply is shorted, take the maximum short-circuit current that either the i/o or core supplies produce. call this current i pslim . in this case, the power dissi- pation in the mosfet is i pslim 2 x r ds(on) . during power-up, the i/o voltage comes up first, and the core power supply fails to turn on. the mosfet is in linear regulator mode, supporting the core full-load current, as well as the charging of the core output capacitor. for most practical cases, the power charging the core output capacitor can be ignored. the power dissipation in the mosfet for this case is (v i/o - v core ) x i core , where v i/o is the regulated i/o volt- age, v core is the regulated core voltage, and i core is the core full-load current. during power-up, the core voltage comes up first, and the i/o power supply fails to turn on. the mosfet turns on hard, keeping the i/o voltage close to the core voltage. the mosfet in this case supports the i/o load current, as well as the charging of the i/o output capacitor. for most practical cases, the power charging the i/o output capacitor can be ignored. since the i/o voltage never reaches its final value, the i/o load current might be off and the power dissipation in the mosfet is minimal. however, assuming the worst-case condition that the i/o load draws its full-load current, the power dissipation in the mosfet would be i i/o 2 x r ds(on) , where i i/o is the i/o full-load current. the worst-case single-shot power dissipation in the mosfet is the maximum value from the steps above and for a maximum duration of t fault . 7) next, select the mosfet that can take this single pulse energy without going over its maximum junc- tion temperature rating. the maximum mosfet junction temperature can be calculated as follows: t j = t amb + p pulse x z ja where t j is the junction temperature, t amb is the ambient temperature, p pulse is the single-shot power dissipation calculated in step 6 above, and z ja is the junction-to-ambient thermal impedance of the selected mosfet for a single pulse of t fault duration. z ja is specified in all typical mosfet data sheets. example: i/o = 3.3v, i/o power supply has a current limit (i i/o(lim )) of 6a, i/o full-load current is 3a. core is 1.8v, core power supply has a current limit (i core(lim) ) of 6a, core full-load current is 4a. v cc = 5v + 0.5v. core and i/o voltages must track to within 400mv. choose a si9428dy (n-channel mosfet, v ds max = 20v, r ds(on) at +25 c = 0.04 ? at v gs = 2.5v, r ds(on) at +125 c = 1.5 x r ds(on) at 25 c, from the mosfet data sheet, v gs max = 8v).
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics ______________________________________________________________________________________ 15 from step 5: the maximum v i/o and v core differential voltage = (i core(lim) ) x (r ds(on) ) = 6a x 0.04 ? x 1.5 = 360mv. from step 6 (first bullet): power dissipation = i pslim 2 x r ds(on) = (6a) 2 x 0.04 ? x 1.5 = 2.16w. from step 6 (second bullet): power dissipation = (v i/o - v core ) x i core = (3.3v - 1.8v) x 4a = 6w. from step 6 (third bullet): power dissipation = i i/o 2 x r ds(on) = (3a) 2 x 0.04 ? x 1.5 = 0.54w. so, the worst-case power dissipation in the mosfet is 6w for a maximum duration of 20ms. from the si9428dy data sheet, under the normalized thermal transient impedance curve (figure 12), the z ja is 0.05 x +70 c/w for a single pulse. the worst-case junction temperature of the mosfet at +85 c ambient temper- ature is: t j = t amb + p pulse x z ja = +85 c + 6w x 0.05 x +70 c/w = +106 c programming the core voltage see the application circuit examples in figures 9 and 10. the following explains constraints on the core voltage. the high-side constraint requires that the core regula- tor maintain a minimum voltage during normal opera- tion. the low-side limit requires that the core regulator hold the core voltage such that the voltage difference from i/o to core does not exceed the processor s maximum allowable voltage difference: to calculate the high-side limit, set the maximum core voltage set point at the minimum system core voltage minus the total system tolerance: coreset max = core min - tol (tol = total tolerance) calculate the low-side constraint by taking the maxi- mum system i/o voltage, subtracting the maximum allowable i/o to core difference and adding the total system tolerance. coreset min = i/o max - ? v i/oc + tol the following comprise the sources for the total system tolerance: resistor mismatch max5039/MAX5040 reference error loop gain error for example: v core = 1.800 5% v i/o = 3.300 5% maximum voltage that i/o can exceed core without damage to the processor: ? v i/oc = (v i/o - v core ) max = 2v system gain = 200v/v normalized thermal transient impedance, junction to ambient square wave pulse duration (s) normalized effective transient thermal impedance 2 1 0.1 0.01 1 1 0 600 0.0001 0.001 0.01 0.1 duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse 100 1. duty cycle, d = 2. per unit base = r thja = + 70 c/w 3. t jm - t a = p dm z thja (t) notes: 4. surface mounted p dm t 1 t 2 t 1 t 2 figure 12. normalized thermal transient impedance
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 16 ______________________________________________________________________________________ resistor mismatch: if the core set point is 1.6v, the ratio is 800mv/1600mv = 0.5. with 1% resistors, the resistor error is: error res (%) = 1% x {2 x (1 - 0.5)} = 1% max5039/MAX5040 reference error: 2.0%. loop gain error: loop gain error is due to the finite sys- tem gain. a loop gain of 200 yields a 0.5% gain error. calculate the maximum and minimum regulator core voltage set point as follows: coreset max = core min - tol = (1.8v - 5%) - 3.5% = 1.8v x 91.5% = 1.647v coreset min = i/o max - ? v i/oc + tol = ((3.3v + 5%) - 2v) + 3.5% = (3.465v - 2v) x 103.5% = 1.465v x 103.5% = 1.516v set the core voltage set point (v regnom ) between 1.516v and 1.647v and as close to the upper value (1.647v) as possible. connect the midpoint of a voltage-divider between core and gnd to core_fb, as shown in the typical application circuit. set the midpoint voltage to 800mv for a maximum core voltage set point of 1.647v. choose a value for r2 of 10k ? . calculate r1 with the following equation: example: using a standard 10.0k ? (1%) resistor in series with a 604 ? (1%) resistor yields negligible resolution error. programming uvlo voltage see the application circuit examples in figures 9 and 10. the max5039/MAX5040 provide a user-programmable undervoltage lockout feature through the uvlo pin. when using a resistor-divider, r7 and r8, from an input voltage rail (v in ) to uvlo to gnd, the user-program- mable uvlo feature allows v in to get to a certain value before max5039/MAX5040 turn the system power sup- plies on together. v in is usually the input voltage to the system power supplies and it can be the same as v cc . the uvlo pin also provides the system a way to turn on/off the system power supplies (see the uvlo sec- tion). choose the uvlo trip point such that the mini- mum v in voltage exceeds the maximum uvlo rising threshold. follow the guidelines below to program the uvlo voltage: 1) determine the v in tolerance; 5% is common. 2) determine the v uvlo rising threshold tolerance: undervoltage lockout rising trip threshold, v uvcc , tolerance: 1.230v 2.5% programming resistor tolerance: pick a 1% resistor or better (2% over temperature) resistor-divider stack-up tolerance: 1% maximum for 1% resistors resistor value resolution: 0.5% (can be zero if exact resistor value is available) extra margin: 1% total = 7% 3) set v uvlo nominal value to: v in nominal value - (v in tolerance + v uvlo tolerance) 4) calculate r7 using the equation: where r 8 is typically 10k ? . example: v in nominal value = 5v, v in tolerance = 5%; set the v uvlo nominal value to 5v - (5% + 7%) = 4.4v. choose r8 = 10.0k ? , 1%: r v v r v v kk uvlonom uvcc 718 44 1 230 110 258 =? ? ? ? ? ? ? =? ? ? ? ? ? ? = . . . ?? r v v r uvlonom uvcc 718 =? ? ? ? ? ? ? r v v r v v kk regnom c ref 112 1 647 08 110 106 =? ? ? ? ? ? ? ? ? =? ? ? ? ? ? ? = _ . . . ?? r v v r regnom c ref 112 =? ? ? ? ? ? ? ? ? _ error res tol ratio ratio mv v res regnom (%) _ ; = ? () {} = 21 800 table 1. error summation error amount (%) divider mismatch (1% resistor) 1.0 reference voltage 2.0 loop gain error 0.5 total = tol 3.5%
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics ______________________________________________________________________________________ 17 linear regulator compensation see the application circuit examples in figures 9 and 10. the external mosfet, together with the feedback resis- tor-divider, r1 and r2, from core to core_fb to gnd, and ndrv form a linear regulator loop. this linear regu- lator should be compensated for stable operation. note: the linear regulator spends most of its time in idle mode. it operates in transient mode and regulation mode only during system power-up/power-down, brownout, and occasional system load transient conditions. loop stability applies when the linear regulator is in the regula- tion mode. follow these simple guidelines to stabilize the linear loop: (see the core regulator loop bode plot in the typical operating characteristics ). 1) place c1, a 100nf, ceramic capacitor (x5r, x7r type or better) from ndrv to gnd. 2) select r1 and r2, a resistor-divider from core to core_fb to gnd to set the linear regulator output regulation voltage (see the programming core voltage section). 3) place r3 and c2, an rc network from core_fb to ndrv. set r3 = r1 and calculate c2 as follows: 4) place r4, a preload resistor from core to gnd. calculate r4 as follows: where gfs is the transconductance of the external mosfet, q1, as specified in its data sheet and i d is the current where gfs is specified. r4 must be sized to properly handle its power dissipation. example: core power supply = 1.8v, v regnom = 1.6v, c core = 100f, q 1 = si9428 (vishay siliconix): r1 = r2 = r3 = 10.0k ? , 1% use 1.5nf standard value. from the si9428 data sheet, gfs = 24s at i d = 6a: in figures 9 and 10, a resistor value of 50 ? is used for r4 for extra margin. programming i/o_sense voltage (MAX5040 only) see the application circuit examples in figures 9 and 10. i/o_sense is used to monitor the i/o output voltage or any other voltage. the result is reported by the pok out- put signal. choose the i/o_sense trip point such that the minimum monitored voltage at i/o_sense exceeds the maximum i/o_sense rising threshold. follow the guidelines below to program the i/o_sense voltage: 1) determine the tolerance of the output voltage to be monitored, vo: 5% is common. 2) determine v i/o_sense rising threshold tolerance: i/o sense trip-point threshold, v i/o_ref , tolerance: 1.230v 2.5% programming resistor tolerance: pick 1% resistor or better (2% over temperature) resistor-divider stackup tolerance: 1% maximum for 1% resistors resistor value resolution: 0.5% (can be zero if exact resistor value is available) extra margin: 1% total = 7% 3) set vi/o_sense rising nominal value to: vo nominal value - (vo tolerance + vi/o_sense tolerance). 4) calculate using the following equation: where r6 is typically 10k ? . example: v i/o nominal value = 3.3v, set v i/o_sense nominal value to 3.3v - (5% + 7%) = 2.904v. choose r6 = 10.0k ? , 1%: r v v r r v v kk i o sensenom i o ref 516 5 2 904 1 230 110 1361 =? ? ? ? ? ? ? ? ? =? ? ? ? ? ? ? = /_ /_ . . . ?? r v v r i o sensenom i o ref 516 =? ? ? ? ? ? ? ? ? /_ /_ r gfs v hz c i sv hz f a core co re d 4 2 250 24 1 6 2 250 100 6 78 = = . ? c khz k nf 2 1 210 10 16 = () = ? . r gfs v hz c i core core d 4 2 250 c khz r 2 1 210 3 =
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics 18 ______________________________________________________________________________________ powerpc/ dsp/asic i/o power supply in in out out v cc v in uvlo gnd core_fb core sdo ndrv i/o i/o core v i/o v core core power supply shdn shdn max5039 typical operating circuit top view core core_fb gnd 1 2 8 7 ndrv i/o v cc uvlo sdo max 3 4 6 5 max5039 1 2 3 4 5 10 9 8 7 6 ndrv i/o core core_fb gnd uvlo v cc sdo MAX5040 max pok i/o_sense pin configurations chip information transistor count: 1272 process: bicmos
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics ______________________________________________________________________________________________________ 19 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 8lumaxd.eps package outline, 8l umax/usop 1 1 21-0036 j rev. document control no. approval proprietary information title: max 0.043 0.006 0.014 0.120 0.120 0.198 0.026 0.007 0.037 0.0207 bsc 0.0256 bsc a2 a1 c e b a l front view side view e h 0.60.1 0.60.1 ? 0.500.1 1 top view d 8 a2 0.030 bottom view 1 6 s b l h e d e c 0 0.010 0.116 0.116 0.188 0.016 0.005 8 4x s inches - a1 a min 0.002 0.95 0.75 0.5250 bsc 0.25 0.36 2.95 3.05 2.95 3.05 4.78 0.41 0.65 bsc 5.03 0.66 6 0 0.13 0.18 max min millimeters - 1.10 0.05 0.15 dim
max5039/MAX5040 voltage-tracking controllers for powerpc, dsps, and asics maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 i rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1

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